The present invention relates to a semiconductor integrated circuit and a test system thereof.
Built-in self test (hereinafter, will be referred to as BIST) circuits are incorporated into semiconductor integrated circuits including memories, and the BIST circuits are used to conduct BISTs to identify the presence or absence of failures in memories and locate failures.
BIST circuits include a comparator BIST circuit which compares a data expected value equal to written data and data read from a memory and identifies the presence or absence of a failure, and a compressor BIST circuit which compresses, in the BIST circuit, data read from a memory and identifies the presence or absence of a failure by using the compression result.
The following will describe BIST operations in a conventional semiconductor integrated circuit including a comparator BIST circuit.
A BIST control circuit in the BIST circuit controls a data generator, an address generator, a control signal generator, and a result analyzer. A BIST target memory is included in a block called a memory collar, together with logical elements required for BIST operations.
The memory is fed with written data generated from the data generator, address data generated from the address generator, and a control signal generated from the control signal generator.
Data outputted from the memory is temporarily stored in a capturing register disposed on the output side of the memory. An output from the capturing register is compared by a comparator with a data expected value generated from the data generator, and the comparison result is held in a flag register. An output from the flag register is inputted to the result analyzer in the BIST circuit, and a final BIST result is outputted.
When conducting BISTs on a plurality of memories in a single BIST circuit, flag data from the memories is inputted to the result analyzer, the presence or absence of a failure is determined based on the overall BISTs, and then a final BIST result is outputted.
Further, when failure diagnosis is conducted with a BIST circuit to extract possible locations of failures in memories, output data is serially extracted from the plurality of memories to the outside and is observed by an external tester.
When using the aforementioned comparator BIST circuit, the capturing registers for capturing memory outputs in the memory collars and the flag registers for receiving outputs from the comparators in the memory collars are all serially connected. Moreover, the registers, an address register fed with an address from an address generating circuit in the BIST circuit, and the flag register of the overall BIST are all serially connected, so that a circular shift path is formed in the overall BIST circuit.
The shift path is used in failure diagnosis and register values are shifted out according to the timing of reading. Since the shift path is formed in a circulating manner, the circuit can recover to the suspended state of the BIST operation after the end of shifting-out.
After that, the BIST is restarted and register values are shifted out on the subsequent timing of reading. By repeatedly suspending the BIST operation, shifting out register values, and restarting the BIST operation, it is possible to read states in the memories. Based on obtained results, a fail bit map indicating the bit position of a failure in the cell array of the memory is produced and failure analysis is conducted.
However, such a conventional technique requires serial reading of all the BIST results and thus register values have to be shifted out also from memories other than the target of failure diagnosis. Therefore, BISTs conducted on a large number of memories in a single BIST circuit result in an extremely long failure diagnosis time.
Further, for example, when similar failed patterns consecutively appear, it is necessary to detect a failure, suspend the BIST operation, shift out a register value, and restart the BIST operation at each address, resulting in an extremely long failure diagnosis time.
Moreover, when BIST results are shifted out, the shift outputs are observed and compared with an expected value in the external tester. The observation and comparison are restricted because the operating speed of the external tester is lower than the operating speed (actual speed) of a semiconductor integrated circuit in an actual operation.
Therefore, it has been difficult to conduct failure diagnosis at the actual speed of the semiconductor integrated circuit and it has not been possible to detect possible failures which can be detected only by failure diagnosis at the actual speed.